This invention relates, in general, to pad arrays, and more particularly to pad configurations which can accommodate more than one pad pitch.
The pad array is an external interface of a semiconductor chip for coupling signals to the semiconductor chip. Testing semiconductor die at wafer probe is performed with a probe card having probe needles which contact the semiconductor die on the pad array. Each probe needle contacts a pad on the semiconductor die. Most semiconductor die are placed in some form of package. A package has electrical interconnects which couple to the pads on the semiconductor die.
High pad counts on semiconductor die are expected as device densities and circuit functionality increase due to processing advances. Pad counts are limited by several factors. First, a minimum pad size is determined by package interconnect or probe card needles. The pad size must be large enough to support adequate contact and insure good yield. Second, pad spacing or pad pitch (the distance between pads) must be wide enough to prevent package interconnect or probe card needles from shorting together. Finally, the number of pads is limited by physical space on the semiconductor die. Staggering pads is commonly used to provide minimum pad sizes at a minimum pad pitch. It should be noted that package assembly yields decrease and probe card costs increase with increasing pad counts due to the added complexities involved with finer geometries.
Defacto standards have been established on pad size and pad pitch. Standardization is mainly due to the large number of semiconductor, package, and probe card vendors which sell products to each other and also to keep costs down. Pad pitch has been standardized in 25 micron increments. For example, probe cards can be purchased which contact semiconductor pads having 75 micron, 100 micron, 125 micron, 150 micron, etc. pad pitches. Semiconductor die are built having a predetermined pad size and pad pitch. Probe cards and packages are built to couple to the predetermined pad size and pad pitch.
All semiconductor manufacturers offer a uniform pad size with a uniform pad pitch, this is not efficient when offering a wide variety of packages, process technologies, and different pad counts. For example, a gate array manufacturer offers several different size gate arrays for a given process flow. Each process flow will have a different minimum pad size and pad pitch. Within a given process flow different pad sizes and pad pitches may be necessary to accommodate different styles of semiconductor packages. Each different gate array (from a family of gate arrays) corresponding to a specific process flow will have a unique probe card built for testing purposes. A great deal of time and money can be spent developing different gate arrays, packages, probe cards, and modifying computer aided design tools to meet customers varying pad configuration needs.
Customers needing to vary pad pitch or pad size on a gate array chip (for design or packaging reasons) have no alternatives other than building a full custom array having the desired pad sizes and pad pitches. A custom probe card and custom package may also have to be built, driving up costs and development time to intolerable levels.
A core limited gate array design is a design wherein the interior core of a die is fully utilized but not all pads available are used. Packaging yields are typically a function of pin count and the minimum spacing between package to pad interconnect. High pin counts and smaller interconnect spacings will have the lowest yields. Packaging yields could be increased if non-minimum pad spacings could be used in a core limited gate array design.
A pad limited design is a design wherein the interior core of a die is not fully utilized but all the pads are used. A worst case scenario for a core limited design occurs when a user must move up to a larger gate array size for extra pads even though most of the interior core of the gate array will go unused. Because the pad size and pad pitch is fixed, adjustments cannot be made to take advantage of varying interconnect technology without redesigning the gate arrays.
There is very little interchangeability between process flows. Packages developed for a specific pad pitch and pad size, typically, cannot be used in the next generation process flow (which will have a different pad size and pad pitch). Probe cards have even less chance for use in different process flows.
Uniform pad size and pad pitch severely limits flexibility, increases costs, and does not take advantage of previous developments. It would be of some importance to provide a pad size and pad pitch configuration which is adjustable. An adjustable pad array would shorten development time, minimize need for customization, reduce cost, allow current developments to be used with next generation process flows, and give customers a choice on using different package technologies.